The system-on-chips (SoC) with implemented Cortex-A5 cores include a. Compared to these older cores, the Cortex-A5 offers the advantage of the more modern instruction set ARMv7 compared to ARMv4 / v5 (ARM9) or ARMv6 (ARM11) as well as VFPv3 and NEON- SIMD extensions. The Cortex-A5 was introduced as the more energy-efficient successor to the ARM9 and ARM11 cores for entry-level and mid-range mobile devices. The clock frequencies in a 40 nm process from TSMC reach up to 1 GHz. It has a computing power of 1.57 DMIPS / MHz and has a 4-64 kB L1 cache for commands and data as well as an optional 16 kB to 1 MB L2 cache. The ARM Cortex-A5 MPCore presented in 2009 is a 32-bit multicore processor with up to 4 cache-coherent Cortex-A5 cores, each of which implements the ARMv7-A instruction set.
The SCU ensures the L1 data cache coherence. The multiprocessor ARM Cortex-A9 MPCore has up to four cache-coherent Cortex-A9 processor cores that are under the control of the Snoop Control Unit (SCU). The Cortex-A9 is the first member of the Cortex-A family that can be used in both uniprocessor and multiprocessor configurations. The clock frequencies in a 45 nm process from TSMC range between 800 MHz and 2 GHz. The processor has a computing power of 2.5 DMIPS / MHz and has a 32 kB L1 cache for commands and data as well as a 128 kB to 8 MB L2 cache. The Cortex-A9 is a superscalar dual issue out of order design. It can execute 32-bit ARM commands, 16- and 32-bit thumb commands and 8-bit Java bytecodes. The ARM Cortex-A9 introduced in 2007 is a 32-bit microprocessor that implements the ARMv7-A architecture.